About Me

Hi! I am a CS PhD student at University of Illinois Urbana-Champaign, Siebel School of Computing and Data Science. I finished my undergraduate program at Shanghai Jiao Tong University, Zhiyuan College, ACM class, majoring in Computer Science.

My research primarily focuses on security and privacy and agent security. Specifically, I am mainly working on ML Security, building zero-knowledge proof systems and zkSNARKs for ML.

Papers

• Efficient Anonymous Credentials by Dynamic ZKPs
  • Submitted to IEEE S&P ’27
• Prezta: Provable Remote Execution of Zero-Trust Authorization using SNARKs [Paper]
  • Zhongjing Wei, Osaid Muhammad Ameer, Yupeng Zhang, Nikita Borisov
  • USENIX Security ’26

Education

University of Illinois Urbana-Champaign

• PhD in Computer Science, advised by Prof.Yupeng Zhang.
• Sep. 2024 - Present

Shanghai Jiao Tong University

• Honors Bachelor of Engineering (B.Eng. Hons) in Computer Science
• Member of ACM Honors Class, which is an elite CS program for top 5% talented students, advised by Prof. Yong Yu.
• Sep. 2020 - Jun. 2024

Research Experience

University of Illinois Urbana-Champaign (SPR&I)

• CS PhD student. Advised by Prof.Yupeng Zhang.
• Sep. 2024 - Present

University of California, Berkeley

• Research Assistant. Advised by Prof.Dawn Song.
• Jan. 2023 - May. 2024
• Projects
  • Efficient privacy-preserving serving of large language models
  • LLM serving speedtest
  • Programming framework for distributed applications with access control
  • LLM-based generated Knowledge Graph for DeFi

Shanghai Jiao Tong University (SAIL lab)

• Research Assistant. Advised by Prof.Chao Li.
• Jul. 2022 - Jul. 2023
• Projects
  • Edge streaming graph computing

Selected Projects

Mx Compiler [Java, LLVM IR, RISC-V, Antlr]

• Sep. 2021 - Feb. 2022
• Developed a compiler that compiles C-and-Java-like language (Mx*) to Assembler.
• Implemented the module that converts the AST to LLVM IR, and verified the correctness of IR outputs with clang.
• Implemented optimizations such as constant propagation and loop unrolling, that outperformed GCC O1.

RISC-V CPU [Assembly, FPGA, Verilog, RISC-V]

• Sep. 2021 - Dec. 2021
• Designed a RISC-V CPU that supports RV32I Base Integer Instruction Set V2.2 (2.1-2.6).
• Designed a modified Tomasulo structure that can dynamically schedule instructions and allow out-of-order execution.

Honors and Awards

• Zhiyuan Honorary Scholarship, Shanghai Jiao Tong University (2020, 2021, 2022)
• Academic Excellence Scholarship, Shanghai Jiao Tong University (2021, 2022, 2023)

Teaching Experience

• Programming(CS1954), Teaching Assistant, Shanghai Jiao Tong University, Fall 2021
• Data Structure(CS1951), Teaching Assistant, Shanghai Jiao Tong University, Spring 2022
• Principle and Practice of Computer Algorithms(CS1952), Teaching Assistant, Shanghai Jiao Tong University, Summer 2022
• Computer Security(CS461/ECE422), Teaching Assistant, University of Illinois Urbana-Champaign, Fall 2026

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